The present application relates to a semiconductor structure and a method of forming the same. More particularly, the present application relates to a semiconductor structure including a resistive random access memory stack that is present on a surface of a faceted drain-side structure of a functional gate structure that is located on a fully depleted semiconductor channel material layer of a semiconductor-on-insulator (SOI) substrate.
Many modern day electronic devices contain electronic memory. Electronic memory may be volatile memory or non-volatile memory. Non-volatile memory retains its stored data in the absence of power, whereas volatile memory loses its stored data when power is lost. Resistive random access memory (ReRAM or RRAM) is one promising candidate for the next generation of non-volatile memory due to its simple structure and its compatibility with complementary metal-oxide-semiconductor (CMOS) logic fabrication processes.
For oxide ReRAMs, electroforming of a current conducting filament is needed. This process relies on randomness and thus the position of the filament of the oxide ReRAM is not well controlled. This results in a higher forming voltage as the ReRAM cell is scaled and higher device variability. Moreover, bipolar ReRAM is preferred, especially for neuromorphic computing which requires resistance state updates in both directions by voltages pulses with opposite polarity.